Three dimensional integrated circuits (“3D ICs) are a highly anticipated emerging technology, and are viewed as having the potential to provide numerous benefits over traditional two dimensional integrated circuits. For example, 3D ICs may allow the production of circuits that include a larger number of components (e.g., transistors) in the same or smaller area as a two dimensional circuit. 3D ICs may also permit heterogenous integration, wherein different circuit layers are manufactured with different processes or even on different wafers—opening avenues to greater levels of circuit customization. Shorter interconnections between components may also be possible in 3D ICs, potentially reducing power consumption.
Several methods for manufacturing 3D ICs are known, including monolithic manufacturing, wafer-on-wafer manufacturing, die-on-wafer manufacturing, and die-on-die manufacturing. Monolithic fabrication of 3D ICs generally involves providing a first layer of circuitry and/or electronic components, depositing an inorganic material such as silicon on the first layer, and forming a second layer of circuitry/components on the first layer and/or electronic components by processing the deposited semiconductive material. In contrast, the wafer-on-wafer approach forms 3D ICs by building electronic components on two separate inorganic (e.g., silicon) semiconductor wafers, which are subsequently aligned, bonded, and diced to form 3D ICs. The wafer-on-die and die-on-die are similar to the wafer-on-wafer approach, except that one or both of the wafers is/are diced prior to bonding. For example, in the wafer-on-die approach, one of the wafers may be diced into singulated dice, which may be individually aligned and bonded onto die sites of the intact wafer. In the die-on-die approach, both wafers may be diced into singulated dice, which may then be aligned and bonded. In any of these approaches, the wafers and/or dies may be thinned before or after bonding.
Although existing processes for manufacturing 3D ICs are useful, they can present various challenges. For example, the quality of the deposited inorganic material produced during monolithic fabrication may be less than the quality of semiconductive materials provided in wafer form, which may result in reduced performance. The wafer-on-wafer, wafer-on-die, and die-on-die approaches may address this issue by forming electronic components in individual inorganic semiconductive wafers, e.g., silicon wafers. However, those processes may require expensive and time consuming alignment, bonding, and (optional) thinning operations. The number of layers that can be used to form 3D ICs with the wafer-on-wafer, wafer-on-die, and die-on-die approaches may also be limited. It may be necessary to perform such processes in a semiconductor fabrication facility in order to produce viable 3D ICs.
Thus, known processes for producing 3D ICs may entail a long design cycle, the production of expensive lithography masks, long wait times, and/or high fees for a foundry run. Such processes may therefore be economically undesirable when relatively few copies of a 3D IC are to be produced, as may be the case during the design, prototype, and test phases of circuit development.
Although the following detailed description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.